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CY7C028V-15AC 参数 Datasheet PDF下载

CY7C028V-15AC图片预览
型号: CY7C028V-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 32K / 64K X 16/18双端口静态RAM [3.3V 32K/64K x 16/18 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 456 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Characteristics
Over the Operating Range
[6]
(continued)
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
Parameter
Description
Min
t
HD
t
HZWE[9, 10]
t
LZWE[9 ,10]
t
WDD[36]
t
DDD[36]
Busy Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[13]
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
t
SAA
-15
Max
10
3
30
25
15
15
15
15
5
0
13
15
15
15
10
5
5
15
10
5
5
5
0
15
3
Min
0
0
-20
Max
12
3
40
30
20
20
20
16
5
0
17
20
20
20
12
5
5
20
Min
0
-25
Max
Unit
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Setup for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
ns
15
50
35
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
20
20
ns
ns
ns
ns
ns
ns
25
ns
Interrupt Timing
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
Semaphore Timing
Data Retention Mode
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within
V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the mini-
mum operating voltage (3.0 volts).
Timing
Data Retention Mode
V
CC
3.0V
V
CC
>
2.0V
3.0V
t
RC
V
IH
CE
V
CC
to V
CC
– 0.2V
Parameter
ICC
DR1
Test Conditions
At VCC
DR
= 2V
Max
50
Unit
μA
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to
waveform.
12. Test conditions used are Load 1.
13. t
BDD
is a calculated parameter and is the greater of t
WDD
–t
PWE
(actual) or t
DDD
–t
SD
(actual).
14. CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25° C. This parameter is guaranteed but not tested.
Document #: 38-06078 Rev. *B
Page 8 of 18