CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions
Name
A
0
, A
1
, A
TQFP
37,36,32,
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
BGA
fBGA
I/O
Description
R6,P6,A2,
Input-
Address Inputs used to select one of the
P4,N4,
A10,B2,
Synchronous
256K address locations.
Sampled at the rising
A2,B2,
B10,N6,P3,P4,
edge of the CLK if ADSP or ADSC is active
C2,R2,
P8,P9,P10,
LOW, and CE
1
, CE
2
, and CE
3 [2]
are sampled
A3,B3,C3,
T3,T4,A5,B5, P11,R3,R4,R8,
active. A1: A0 are fed to the two-bit counter..
R9,R10,R11
C5,
T5,A6,B6,C6,
R6
L5,G5,
G3,L3
H4
B5,A5,A4,
B4
B7
Input-
Byte Write Select Inputs, active LOW.
Synchronous Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
Synchronous When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are
written, regardless of the values on BW
X
and
BWE).
Input-
Byte Write Enable Input, active LOW.
Sam-
Synchronous pled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input.
Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
BW
A,
BW
B
BW
C,
BW
D
GW
93,94,95,
96
88
BWE
87
M4
A7
CLK
89
K4
B6
CE
1
98
E4
A3
Input-
Chip Enable 1 Input, active LOW.
Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device.
ADSP is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled
Synchronous on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on
Synchronous the rising edge of CLK. Used in conjunction with
CE
1
and CE
2
to select/deselect the device.Not
available for AJ package version.Not
connected for BGA. Where referenced, CE
3
is
assumed active throughout this document for
BGA.
Input-
Output Enable, asynchronous input, active
Asynchronous
LOW.
Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during
the first clock of a read cycle when emerging
from a deselected state.
Input-
Advance Input signal, sampled on the rising
Synchronous
edge of CLK, active LOW.
When asserted, it
automatically increments the address in a burst
cycle.
CE
2[2]
97
-
B3
CE
3[2]
92
-
A6
OE
86
F4
B8
ADV
83
G4
A9
Document #: 38-05237 Rev. *D
Page 6 of 36
CYPRESS [ CYPRESS SEMICONDUCTOR ]
