CY7C1399
Switching Characteristics
Over the Operating Range
[5]
7C1399–12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
7C1399–15
Min.
15
Max.
7C1399–20
Min.
20
Max.
7C1399–25
Min.
25
Max.
7C1399–35
Min.
35
Max.
Unit
ns
35
3
35
10
0
7
3
8
0
35
35
20
20
0
0
20
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
3
ns
ns
Description
Min.
12
Max.
12
3
12
5
0
5
3
6
0
12
12
8
8
0
0
8
7
0
7
3
3
15
10
10
0
0
10
8
0
0
3
0
3
15
3
15
6
0
6
3
7
0
15
20
12
12
0
0
12
10
0
7
3
20
3
20
7
0
6
3
7
0
20
25
15
15
0
0
15
11
0
7
3
25
25
8
7
8
25
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[8]
WE HIGH to Low Z
[6]
WRITE CYCLE
[8, 9]
7
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
L
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
Min.
2.0
200
20
0
t
RC
Max.
Unit
V
µA
µA
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and capacitance C
L
= 30 pF.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified with C
L
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
