CY7C185
Switching Waveforms
(continued)
rite Cycle No. 2 (CE Controlled)
[12,13,14]
t
WC
ADDRESS
CE
1
t
SA
CE
2
t
AW
WE
t
SD
DATA I/O
DATA
IN
VALID
C185–9
t
SCE1
t
SCE2
t
HA
t
HD
Write Cycle No. 3 (WE Controlled, OE LOW)
[12,13,14,15]
t
WC
ADDRESS
CE
1
CE
2
t
SCE1
t
SCE2
t
AW
t
SA
WE
t
SD
DATA I/O
NOTE 13
t
HZWE
DATA
IN
VALID
t
LZWE
C185–10
t
HA
t
HD
Notes:
14. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
15. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05043 Rev. **
Page 6 of 11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
