CY7C4255
CY7C4265
Switching Waveforms (continued)
Reset Timing [17]
t
RS
RS
t
RSR
REN,WEN,
LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
[18]
OE=1
Q
Q
0 – 17
OE=0
4255–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
17
t
ENS
[19]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
[19]
t
A
t
A
Q –Q
D
0
D
1
0
17
t
OLZ
t
OE
OE
4255–9
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
19. When t > minimum specification, t (maximum) = t + t . When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
+
SKEW2
FRL
CLK
SKEW2
SKEW2
FRL
CLK
SKEW2
CLK
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW2
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06004 Rev. *B
Page 8 of 22
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