CY7C4255
CY7C4265
AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
3.0V
GND
90%
10%
90%
10%
OUTPUT
R2
680Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
4255–4
4255–5
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
410Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Parameter
tS
Description
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Min. Max. Unit
100
8
66.7
10
40
15
28.6 MHz
20
tA
Data Access Time
2
10
4.5
4.5
3
2
15
6
2
25
10
10
6
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-Up Time
4
tDH
Data Hold Time
0.5
3
1
1
2
tENS
tENH
tRS
Enable Set-Up Time
4
6
7
Enable Hold Time
0.5
10
8
1
1
2
Reset Pulse Width[12]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
Output Enable to Output in High Z[13]
Write Clock to Full Flag
Read Clock to Empty Flag
15
10
25
15
35
20
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
10
15
25
35
30
60
0
35
65
0
45
75
0
55
85
0
3
7
7
3
8
3
12
12
15
15
20
3
15
15
20
20
25
tOHZ
tWFF
tREF
tPAFasynch
3
3
8
3
3
8
10
10
16
8
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to
12
VCC
)
tPAFsynch
tPAEasynch
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC
8
12
8
10
16
10
16
15
20
15
20
20
25
20
25
ns
ns
ns
ns
)
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
)
tHF
Clock to Half-Full Flag
12
Notes:
10.
11.
C
C
= 30 pF for all AC parameters except for t
.
OHZ
L
L
= 5 pF for t
.
OHZ
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
14.
t
, t
, after program register write will not be valid until 5 ns + t
.
PAFasynch PAEasynch
PAF(E)
Document #: 38-06004 Rev. *B
Page 5 of 22
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