CY7C63001A
CY7C63101A
7.168 to
8.192 ms
8.192 ms
Last write to
Watchdog Timer
Register
No write to WDT
register, so WDR
goes HIGH
Figure 6-4. Watchdog Reset
Execution begins at
Reset Vector 0x00
6.3.2
Watchdog Reset (WDR)
The Watchdog Timer Reset (WDR) occurs when the Most
Significant Bit of the 4-bit Watchdog Timer Register transitions
from LOW to HIGH. Writing any value to the write-only
Watchdog Restart Register at 0x21 clears the timer (firmware
should periodically write to the Watchdog Restart Register in
the ‘main loop’ of firmware). The Watchdog timer is clocked by
a 1.024-ms clock from the free-running timer. If 8 clocks occur
between writes to the timer, a WDR occurs and bit 6 of the
Status and Control Register is set to record the event. A
Watchdog Timer Reset lasts for 8.192 ms, at which time the
microcontroller begins execution at ROM address 0x00. The
USB transmitter is disabled by a Watchdog Reset because the
USB Device Address Register is cleared (otherwise, the USB
Controller would respond to all address 0 transactions). The
transmitter remains disabled until the WDR bit (bit 6) in the
Status and Control Register is reset to 0 by firmware.
6.3.3
USB Bus Reset
register. All logic blocks in the device are turned off except the
USB receiver, the GPIO interrupt logic, and the Cext interrupt
logic. The clock oscillator and the free-running and Watchdog
timers are shut down.
The suspend mode is terminated when one of the following
three conditions occur:
1. USB activity
2. A GPIO interrupt
3. Cext interrupt
The clock oscillator, GPIO, and timers restart immediately
upon exiting suspend mode. The USB engine and microcon-
troller return to a fully functional state no more than 256
µs
later. Before servicing any interrupt requests, the microcon-
troller executes the instruction following the I/O write that
placed the device into suspend mode.
Both the GPIO interrupt and the Cext interrupt allow the USB
Controller to wake-up periodically and poll potentiometers,
optics, and other system components while maintaining a very
low average power consumption. The Cext Interrupt is
preferred for lowest power consumption.
For Cext to generate an “Instant-on” interrupt, the pin must be
connected to ground with an external capacitor and connected
to V
CC
with an external resistor. A “0” is written to the Cext
register located at I/O address 0x22 to discharge the capacitor.
Then, a “1” is written to disable the open-drain output driver. A
Schmitt trigger input circuit monitors the input and generates
a wake-up interrupt when the input voltage rises above the
input threshold. By changing the values of the external resistor
and capacitor, the user can fine tune the charge rate of the R-
C timing circuit. The format of the Cext register is shown in
Reading the register returns the value of the Cext
pin. During a reset, the Cext pin is HIGH.
b3
Reserved
0
b2
Reserved
0
b1
Reserved
0
b0
CEXT
R/W
1
The USB Controller recognizes a USB Reset when a Single
Ended Zero (SE0) condition persists for at least 8–16
µs
(the
Reset may be recognized for an SE0 as short as 8
µs,
but it is
always recognized for an SE0 longer than 16
µs).
SE0 is the
condition in which both the D+ line and the D– line are LOW.
Bit 5 of the Status and Control Register is set to record this
event. If the USB reset happens while the device is
suspended, the suspend condition is cleared and the clock
oscillator is restarted. However, the microcontroller is not
released until the USB reset is removed.
6.4
Instant-on Feature (Suspend Mode)
The USB Controller can be placed in a low-power state by
setting the Suspend bit (bit 3) of the Status and Control
b7
Reserved
0
b6
Reserved
0
b5
Reserved
0
b4
Reserved
0
Figure 6-5. The Cext Register (Address 0x22)
Document #: 38-08026 Rev. *A
Page 7 of 25
CYPRESS [ CYPRESS SEMICONDUCTOR ]
