CY7C63413C
CY7C63513C
CY7C63613C
Pin Definitions
CY7C63413C
Name
D+, D–
P0[7:0]
I/O
I/O
I/O
40-Pin
1,2
15,26,16
25,17,24
18,23
11,30,12,
29,13,28,
14,27
7,34,8,
33,9,32,
10,31
3,38,4,
37,5,36,
6,35
n/a
48-Pin
1,2
17,32,18
31,19,30
20,29
11,38,12,
37,13,36,
14,35
7,42,8,
41,9,40,
10,39
3,46,4,
45,5,44,
6,43
n/a
Die
1,2
17,32,18,
31,19,30,
20,29
11,38,12,
37,13,36,
14,35
7,42,8,
41,9,40,
10,39
3,46,4,
45,5,44,
6,43
15,34,16,
33,21,28,
22,27
CY7C63513C CY7C63613C
48-Pin
1,2
17,32,18,31,
19,30,20,29
11,38,12,37,
13,36,14,35
7,42,8,41,9,
40,10,39
3,46,4,45,5,
44,6,43
15,34,16,33,
21,28,22,27
24-Pin
1,2
7, 18, 8, 17, 9,
16, 10, 15
5, 20, 6, 19
Description
USB differential data; PS/2 clock and
data signals
GPIO port 0 capable of sinking 7 mA
(typical)
GPIO Port 1 capable of sinking 7 mA
(typical).
GPIO Port 2 capable of sinking 7 mA
(typical).
GPIO Port 3 capable of sinking 12 mA
(typical).
DAC I/O Port with programmable
current sink outputs. DAC[1:0] offer a
programmable range of 3.2 to 16 mA
typical. DAC[7:2] have a program-
mable sink current range of 0.2 to 1.0
mA typical. DAC I/O Port not bonded
out on CY7C63613C. See note on
page 12 for firmware code needed for
unused pins.
6-MHz ceramic resonator or external
clock input
6-MHz ceramic resonator
Programming voltage supply, ground
during operation
Voltage supply
Ground
P1[3:0]
I/O
P2
I/O
n/a
P3[7:4]
I/O
3, 22, 4, 21
DAC
I/O
n/a
XTAL
IN
XTAL
OUT
V
PP
V
CC
Vss
21
IN
OUT
22
19
40
20,39
25
26
23
48
24,47
25
26
23
48
24,47
25
26
23
48
24,47
13
14
11
24
12, 23
Programming Model
14-bit Program Counter (PC)
The 14-bit Program Counter (PC) allows access for up to 8
kilobytes of EPROM using the CY7C63413C/513C/613C
architecture. The program counter is cleared during reset,
such that the first instruction executed after a reset is at
address 0x0000. This is typically a jump instruction to a reset
handler that initializes the application.
The lower eight bits of the program counter are incremented
as instructions are loaded and executed. The upper six bits of
the program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
instruction. The assembler directive “XPAGEON” will cause
the assembler to insert XPAGE instructions automatically. As
instructions can be either one or two bytes long, the assembler
may occasionally need to insert a NOP followed by an XPAGE
for correct execution.
The program counter of the next instruction to be executed,
carry flag, and zero flag are saved as two bytes on the program
stack during an interrupt acknowledge or a CALL instruction.
The program counter, carry flag, and zero flag are restored
from the program stack only during a RETI instruction.
Document #: 38-08027 Rev. *B
Please note the program counter cannot be accessed directly
by the firmware. The program stack can be examined by
reading SRAM from location 0x00 and up.
8-bit Accumulator (A)
The accumulator is the general purpose, do everything
register in the architecture where results are usually calcu-
lated.
8-bit Index Register (X)
The index register “X” is available to the firmware as an
auxiliary accumulator. The X register also allows the processor
to perform indexed operations by loading an index value into
X.
8-bit Program Stack Pointer (PSP)
During a reset, the Program Stack Pointer (PSP) is set to zero.
This means the program “stack” starts at RAM address 0x00
and “grows” upward from there. Note the program stack
pointer is directly addressable under firmware control, using
the MOV PSP,A instruction. The PSP supports interrupt
service under hardware control and CALL, RET, and RETI
instructions under firmware control.
Page 4 of 32
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