CYWUSB6932
CYWUSB6934
Addr: 0x04
7
6
5
Reserved
REG_DATA_RATE
4
3
2
Code Width
1
Default: 0x00
0
Sample Rate
Data Rate
Figure 7-3. Data Rate
Bit
Name
Description
7:3
2
[3]
Reserved
Code Width
These bits are reserved and should be written with zeroes.
The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to inter-
ference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double
data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more
robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted
and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample
Rate (Reg 0x04, bit 0).
The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of
62.5kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg
0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit
PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code
register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate
capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate
enables the user to potentially correlate data using two differing 32 chips/bit PN codes.
The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.
1 = 12x Oversampling
0 = 6x Oversampling
Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double
Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code
is being used with Normal Data Rate.
1
[3]
Data Rate
0
[3]
Sample
Rate
Figure 7-4. Configuration
Addr: 0x05
7
6
5
Reserved
Bit
Name
Description
REG_CONFIG
4
3
2
1
Default: 0x01
0
IRQ Pin Select
7:2
1:0
Reserved
IRQ Pin Select
These bits are reserved and should be written with zeroes.
The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)
10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)
01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)
00 = CMOS Inverted (IRQasserted = 0, IRQ deasserted = 1)
Note:
3. The following Reg 0x04, bits 2:0 values are not valid:
• 001 – Not Valid
• 010 – Not Valid
• 011 – Not Valid
• 111 – Not Valid.
Document 38-16007 Rev. *G
Page 9 of 30
CYPRESS [ CYPRESS SEMICONDUCTOR ]
