DS1225AB/AD
NOTES:
1. WE is high for a read cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during write cycle, the output buffers remain in a high-impedance
state.
3. t
WP
is specified as the logical AND of CE and WE . t
WP
is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. t
DS
are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until
V
CC
is first applied by the user. The expected t
DR
is defined as accumulative time in the absence of
V
CC
starting from the time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on V
CC
.
12. t
WR1
, t
DH1
are measured from WE going high.
13. t
WR2
, t
DH2
are measured from CE going high.
14. DS1225AB and DS1225AD modules are recognized by Underwriters Laboratory (U.L.
) under file
E99151.
DC TEST CONDITIONS
Outputs Open
All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
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DALLAS [ DALLAS SEMICONDUCTOR ]
