DS1225Y
POWER–DOWN/POWER–UP CONDITION
V
CC
V
TP
3.2V
t
F
t
PD
t
REC
t
R
CE
LEAKAGE CURRENT
I
L
SUPPLIED FROM
LITHIUM CELL
DATA RETENTION TIME
t
DR
SEE NOTE 11
POWER–DOWN/POWER–UP TIMING
PARAMETER
CE at V
IH
before Power–Down
V
CC
Slew from V
TP
to 0V
V
CC
Slew from 0V to V
TP
CE at V
IH
after Power–Up
SYM
t
PD
t
F
t
R
t
REC
MIN
0
100
0
2
MAX
UNITS
µs
µs
µs
ms
NOTES
11
(t
A
= 25
°
C)
PARAMETER
Expected Data Retention Time
SYM
t
DR
MIN
10
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during a write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. t
WP
is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DS
is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in a high impedance state during this period.
021998 6/8
DALLAS [ DALLAS SEMICONDUCTOR ]
