DS12887
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of
Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the
SQW pin. The RS0–RS3 bits in Register A establish the square wave output frequency. These
frequencies are listed in Table 1. The SQW frequency selection shares its 1–of–15 selector with the
periodic interrupt generator. Once the frequency is selected, the output of the SQW pin can be turned on
and off under program control with the square wave enable bit (SQWE).
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the
IRQ
pin to go to an active state from once every 500 ms to once
every 122
µs.
This function is separate from the alarm interrupt which can be output from once per
second to once per day. The periodic interrupt rate is selected using the same Register A bits which select
the square wave frequency (see Table 1). Changing the Register A bits affects both the square wave
frequency and the periodic interrupt output. However, each function has a separate enable bit in Register
B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is enabled by the PIE
bit in Register B. The periodic interrupt can be used with software counters to measure inputs, create
output intervals, or await the next needed software function.
UPDATE CYCLE
The DS12887 executes an update cycle once per second regardless of the SET bit in Register B. When
the SET bit in Register B is set to 1, the user copy of the double buffered time, calendar, and alarm bytes
is frozen and will not update as the time increments. However, the time countdown chain continues to
update the internal copy of the buffer. This feature allows time to maintain accuracy independent of
reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar
information is consistent. The update cycle also compares each alarm byte with the corresponding time
byte and issues an alarm if a match or if a “don’t care” code is present in all three positions.
There are three methods that can handle access of the real time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update–ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update–in–progress bit (UIP) in Register A to determine if the update cycle is
in progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer
occurs 244
µs
later. If a low is read on the UIP bit, the user has at least 244
µs
before the time/calendar
data will be changed. Therefore, the user should avoid interrupt service routines that would cause the time
needed to read valid time/calendar data to exceed 244
µs.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than t
BUC
allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within one (t
PI/2
+ t
BUC
) to ensure that
data is not read during the update cycle.
8 of 19
DALLAS [ DALLAS SEMICONDUCTOR ]
