DS1554
DS1554 REGISTER MAP
Table 2
ADDRESS
DATA
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
FUNCTION/RANGE
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
X
X
X
X
X
OSC
W
WDS
AE
AM4
AM3
AM2
AM1
Y
WF
Y
R
X
X
10 Year
X
X
10 MINUTES
10 SECONDS
10 CENTURY
BMB3
ABE
BMB2
Y
BMB1
Y
BMB4
Y
Y
Y
10 M
10 Date
X
X
10 HOUR
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CENTURY
BMB0
Y
DATE
HOURS
MINUTES
SECONDS
Y
BLF
Y
0
Y
0
Y
0
Y
0
RB1
Y
RB0
Y
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CONTROL
WATCHDOG
INTERRUPTS
ALARM DATE
ALARM HOURS
ALARM MINUTES
ALARM SECONDS
UNUSED
FLAGS
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
FT
X
10 DATE
10 HOURS
10 MINUTES
10 SECONDS
Y
0
01-31
00-23
00-59
00-59
AF
X = Unused, read/writable under Write and Read
bit control
FT = Frequency Test bit
OSC
= Oscillator start/stop bit
W = Write bit
R = Read bit
WDS = Watchdog Steering bit
BMB0-BMB4 = Watchdog Multiplier bits
RB0-RB1 = Watchdog Resolution bits
AE = Alarm Flag Enable
Y = Unused, read/writable without Write and Read
bit control
ABE = Alarm in battery Back-up mode enable
AM1-AM4 = Alarm Mask bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 and are read only
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The
OSC
bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Dallas Semiconductor with the clock oscillator turned off,
OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0.
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DALLAS [ DALLAS SEMICONDUCTOR ]
