DS1554
ALARM MASK BITS
Table 3
AM4
AM3
AM2
AM1
ALARM RATE
1
1
1
1
Once per second
1
1
1
0
When seconds match
1
1
0
0
When minutes and seconds match
1
0
0
0
When hours, minutes, and seconds match
0
0
0
0
When date, hours, minutes, and seconds match
When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the
IRQ
/FT pin. The
IRQ
/FT
signal is cleared by a read or write to the Flags Register (Address 7FF0h) as shown in Figure 2 and 3. The
IRQ
/FT signal may be cleared by having the address stable for as short as 15 ns and either
CE
or
WE
active, but is not guaranteed to be cleared unless t
RC
is fulfilled. The alarm flag is also cleared by a read or
write to the Flags Register but the flag will not change states until the end of the read/write cycle and the
IRQ
/FT signal has been cleared.
CLEARING IRQ WAVEFORMS
Figure 2
CLEARING IRQ WAVEFORMS
Figure 3
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DALLAS [ DALLAS SEMICONDUCTOR ]
