DS2152
TABLE OF CONTENTS
1.0
INTRODUCTION ..................................................................................... 4
Block Diagram...............................................................................................................................
Pin List...........................................................................................................................................
Pin Description ..............................................................................................................................
Register Map..................................................................................................................................
6
7
9
13
2.0
3.0
PARALLEL PORT................................................................................... 17
CONTROL, ID, AND TEST REGISTERS ................................................ 18
Payload Loopback .........................................................................................................................
Framer Loopback...........................................................................................................................
Pulse Density Enforcer ..................................................................................................................
Local Loopback .............................................................................................................................
Power-up Sequence .......................................................................................................................
Remote Loopback..........................................................................................................................
23
23
25
27
29
29
4.0
5.0
STATUS AND INFORMATION REGISTERS .......................................... 30
ERROR COUNT REGISTERS ................................................................ 38
Line Code Violation Count Register .............................................................................................
Path Code Violation Count Register..............................................................................................
Multiframes Out of SYNC Count Register ...................................................................................
39
39
40
6.0
7.0
DSO MONITORING FUNCTION ............................................................. 41
SIGNALING OPERATION....................................................................... 44
Processor Based Signaling..........................................................................................................
Hardware Based Signaling..........................................................................................................
44
46
8.0
PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK.......... 47
Transmit Side Code Generation.....................................................................................................
Receive Side Code Generation ......................................................................................................
47
49
9.0
CLOCK BLOCKING REGISTERS .......................................................... 51
10.0 ELASTIC STORES OPERATION............................................................ 52
11.0 FDL/F
S
EXTRACTION AND INSERTION................................................ 53
HDLC and BOC Controller for the FDL.......................................................................................
Legacy FDL Support .....................................................................................................................
D4/SLC-96 Operation....................................................................................................................
53
63
64
12.0 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION 65
13.0 TRANSMIT TRANSPARENCY................................................................ 68
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DALLAS [ DALLAS SEMICONDUCTOR ]
