3D7408
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5.
The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time
t
EQV
, bit 7 (MSB) is valid at
the serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
Pin 3, if unused,
must be allowed to float
if the
device is configured in the serial programming
mode.
SIGNAL IN
IN
PROGRAMMABLE
DELAY LINE
OUT SIGNAL OUT
ADDRESS ENABLE
AE
LATCH
SO
SERIAL OUTPUT
SERIAL INPUT SI
SHIFT CLOCK
MODE SELECT
SC
MD
P0
P1
P2
P3
P4
P5
P6
P7
8-BIT INPUT
REGISTER
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL
INPUTS
P0-P7
DELAY
TIME
PREVIOUS VALUE
NEW VALUE
t
PDX
PREVIOUS VALUE
t
PDV
NEW VALUE
Figure 2: Non-latched parallel mode (MD=1, AE=1)
t
EW
ENABLE
(AE)
t
DSE
PARALLEL
INPUTS
P0-P7
DELAY
TIME
NEW VALUE
t
DHE
t
EDX
PREVIOUS VALUE
t
EDV
NEW VALUE
Figure 3: Latched parallel mode (MD=1)
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
DATADELAY [ DATA DELAY DEVICES, INC. ]
