DM9161
10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver
5.4 Mode, 2 pins
Pin No.
10
Pin Name
PWRDWN
I/O
Description
I Power Down Control
Asserted high to force the DM9161 into power down mode. When in
power down mode, most of the DM9161 circuit block’s power is turned
off, only the MII management interface (MDC, MDIO) logic is available
(the PHY should respond to management transactions and should not
generate spurious signals on the MII)). To leave power down mode, the
DM9161 needs the hardware or software reset with the PWRDWN pin
low
O, Cable Status or Link Status
LI This pin is used to indicate the status of the cable connection when
(D) power up reset latch low (Default)
0 = Without cable connection
1 = With cable connection
This pin is used to indicate the status of the Link connection when power
up reset latch high
0 = Without link
1 = With link
14
CABLESTS
/LINKSTS
5.5 Bias and Clock, 4 pins
Pin No.
47
48
42
43
Pin Name
BGRESG
BGRES
XT2
XT1
I/O
P
O
I/O
I
Description
Bandgap Ground
Bandgap Voltage Reference Resistor 6.8K ohm
Crystal Output; REF_CLK input for RMII mode
Crystal Input
5.6 Power, 13 pins
Pin No.
1,2
9
5
6
46
23,30,39,41
15,33,44
Pin Name
AVDD
AVDD
AGND
AGND
AGND
DVDD
DGND
I/O
P
P
P
P
P
P
P
Description
Analog Receive Power
Analog Transmit Power
Analog Receive Ground
Analog Transmit Ground
Analog Substrate Ground
Digital Power
Digital Ground
Final
Version: DM9161-DS-F05
September 10, 2008
9
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
