DM9301FP
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Diagnostic Port Interface (Continued)
39, 40
MUXCTL1,
MUXCTL0
I
Mux. Control 1 and 0:
Used for testing the DM9301FP Data Paths. Set to zero
for normal operation.
Initiated at an H/W reset. Active high.
DATA PATH
MUXCTL1 MUXCTL0
0
0
Normal, FX to TX and TX to FX
1
0
TX Transmit from TXD[4:0]
TXCLK from TX PLL
TX Receive to RXD[4:0]
RXCLK from TX receive clock
FX Transmit from TXD[4:0]
TXCLK from FX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
TX Transmit from TXD[4:0]
TXCLK from TX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
0
1
1
1
65, 54,
55, 57,
58, 60,
61
92, 91, 89,
88
TPO6, TPO5,
TPO4, TPO3,
TPO2, TPO1,
TPO0
TPI3, TPI2, TPI1,
TPI0,
O
I
Test Port Output:
Reflects the DM9301FP internal status. Selection of
status indicators is made by using TPEN and TPMUX.
Initiated at an H/W reset. Active high.
Test Port Input:
Controls the DM9301FP internal test features. Selection
of input control is made by using TPEN and TPMUX.
TPEN must be true (one) for this signal to take effect.
Initiated at an H/W reset. Active high.
8
Final
Version: DM9301FP-DS-F03
June 06, 2007
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
