I M P L E M E N T A T I O N
Figure below show the typical DI2CS imple-
mentations in system with Standard/Fast and
High-speed devices.
B L O C K D I A G R A M
Figure below shows the DI2CS IP Core block
diagram.
Receive
datai(7:0)
Data
Input
Filter
sdai
datao(7:0)
Shift
VDD
Register
address(1:0)
Output
Register
CPU
sdao
Interface
Send
Data
cs
we
rd
RP
RP
SDA
SCL
Own
address
detection
irq
Control
Register
Control
Logic
RS
RS
RS
RS
Status
Register
sdai
sda
Synchronization
Logic
Input
Filter
scli
sdao
open drain
Master
device
Clock
Stretching
Output
Register
rst
clk
sclo
DI2CS
scli
scl
CPU Interface – Performs the interface func-
tions between DI2CS internal blocks and mi-
croprocessor. Allows easy connection of the
core to a microprocessor/microcontroller sys-
tem.
sclo
open drain
P E R F O R M A N C E
Control Logic – Manages execution of all
commands sent via interface. Synchronizes
internal data flow.
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route (all key features
have been included):
Shift Register – Controls SDA line, performs
data and address shifts during the data
transmission and reception.
Speed
grade
-5
Device
Logic Cells
Fmax
Control Register – Contains five control bits
used for performing all types of I2C Bus
transmissions.
MERCURY
STRATIX
CYCLONE
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
FLEX10KE
MAX 7000AE
MAX 3000A
170
170
170
170
170
170
170
170
170
83
250 MHz
260 MHz
220 MHz
270 MHz
150 MHz
120 MHz
90 MHz
107 MHz
107 MHz
96 MHz
-5
-6
-7
-7
-1
-1
-1
-1
Status Register – Contains seven status bits
that indicates state of the I2C Bus and the
DI2CS core.
Input Filter – Performs spike filtering.
Synchronization Logic – Performs DI2CS
core synchronization.
-5
-5
83
104 MHz
Core performance in ALTERA® devices
Clock Stretching – Performs I2C SCL clock
stretching when DI2CS core is not ready for
next transmission.
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