EL2004/EL2004C
350 MHz FET Buffer
Input Bias Current vs
Temperature
Applications Information
The EL2004 is one member of a family of high
performance buffers manufactured by Elantec.
The 2004 is optimized for speed while others offer
choices of input DC parameters or output drive
or cost. The following table illustrates those
members available at the time of this printing.
Consult the factory for the latest capabilities in
this developing line.
Elantec’s Buffer Family
Slew
Rate
V/ms
Input
Current
(Warm)
Peak Rise
Bandwidth
MHz
Ý
Part
I
Time
ns
OUT
Input Bias Current vs
Input Voltage
mA
ELH0002
200
50
6 mA
2.5 nA
2.5 nA
0.1 nA
400
250
250
250
7
ELH0033 1500
100
350
140
2.9
1.0
2.5
EL2004
EL2005
2500
1500
Recommended Layout Precautions
The very high-speed performance of the EL2004
can only be realized by taking certain precau-
tions in circuit layout and power supply decou-
pling. Low inductance ceramic chip or disc power
supply decoupling capacitors of 0.1 mF or more
should be connected with the shortest practical
lead lengths between the device supply leads and
a ground plane. In addition, it can be helpful to
parallel these with 4.7 mF electrolytics (Tanta-
lum preferred). Failure to follow these precau-
tions can result in oscillation.
2004–9
In applications such as sample and hold circuits
where it is important to maintain low input bias
current over input voltage range, the EL2005
High Accuracy Fast Buffer is recommended.
The input capacitance of EL2004 comprises the
FET device gate-to-source capacitance (which is
a function of input voltage) and stray capaci-
tance to the case. Effective input capacitance can
be minimized by connecting the case to the out-
put since it is electrically isolated. Or, for reduced
radiation, the case may be grounded. The AC
characteristics specified in this data sheet were
obtained with the case floating.
Circuit Operation
The EL2004 is effectively an ideal unity gain am-
plifier with almost infinite input impedance and
about 6X output impedance.
Input Characteristics
The input impedance of a junction FET is a
strong function of temperature and input volt-
12
age. Nominal input resistance of EL2004 is 10
at 25 C junction, but as I doubles every 11 C in
§
§
Offset Voltage Adjustment
The EL2004’s offset voltages have been actively
B
the JFET, the input resistance falls. During
warm-up, self-heating raises the junction temper-
g
laser trimmed at 15V supplies to meet specified
ature up to 60 C or more (without heatsink) so
operating I will be much higher than the data
B
§
limits when the offset adjust pin is shorted to the
offset preset pin. If external offset null is re-
quired, the offset adjust pin should be connected
to a 200X trim pot connected to the negative sup-
ply.
sheet 25 C specification.
§
Another factor which can increase bias current is
input voltage. If the input voltage is more than
20V below the positive supply, the input current
rises exponentially. (See Curve.)
7
ELANTEC [ ELANTEC SEMICONDUCTOR ]
