EBD11ED8ABFB
Byte No.
28
Function described
Minimum row active to row active
delay (tRRD)
-6B
-7A, -7B
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
Minimum active to precharge time
(tRAS)
-6B
-7A, -7B
Module bank density
Address and command setup time
before clock (tIS)
-6B
-7A, -7B
Bit7
0
0
0
0
0
0
1
0
1
Bit6
0
0
1
1
0
0
0
1
0
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
Bit5 Bit4
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
0
1
1
Bit3
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
1
Bit2
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
Bit1 Bit0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
1
1
Hex value
30H
3CH
48H
50H
2AH
2DH
80H
75H
90H
75H
90H
45H
50H
45H
50H
00H
3CH
44H
48H
4BH
30H
2DH
32H
55H
75H
00H
00H
54H
0EH
39H
7FH
Comments
12ns
15ns
18ns
20ns
42ns
45ns
512M bytes
0.75ns*
1
0.9ns*
1
0.75ns*
1
0.9ns*
1
0.45ns*
1
0.5ns*
1
0.45ns*
1
0.5ns*
1
Future use
60ns*
1
68ns*
1
75ns*
1
75ns*
1
12ns*
1
450ps*
1
500ps*
1
550ps*
1
750ps*
1
Future use
29
30
31
32
33
Address and command hold time after
clock (tIH)
0
-6B
-7A, -7B
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data input setup time before clock
(tDS)
-6B
-7A, -7B
Data input hold time after clock (tDH)
-6B
-7A, -7B
Superset information
Active command period (tRC)
-6B
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
-7A, -7B
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
-7A, -7B
Superset information
SPD Revision
Checksum for bytes 0 to 62
-6B
-7A
-7B
34
35
36 to 40
41
42
43
44
45
46 to 61
62
63
64 to 65
Manufacturer’s JEDEC ID code
Continuation
code
Preliminary Data Sheet E0295E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
