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EBD11ED8ABFB-7B 参数 Datasheet PDF下载

EBD11ED8ABFB-7B图片预览
型号: EBD11ED8ABFB-7B
PDF下载: 下载PDF文件 查看货源
内容描述: 1GB无缓冲DDR SDRAM DIMM EBD11ED8ABFB ( 128M的话】 72位, 2家银行) [1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words 】 72 bits, 2 Banks)]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 208 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD11ED8ABFB
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 200 µs and then, execute power on sequence and auto refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VT
VDD, VDDQ
IO
PD
TA
Tstg
Value
–0.5 to +3.6
–0.5 to +3.6
50
18
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
1
Note
Note: DDR SDRAM device specification.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Device Specification)
Parameter
Supply voltage
Symbol
VDD,VDDQ
VSS
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VIX (DC)
VID (DC)
Min
2.3
0
0.49
×
VDDQ
VREF – 0.04
VREF + 0.15
–0.3
–0.3
0.5
×
VDDQ
0.2V
0.36
Typ
2.5
0
0.50
×
VDDQ
VREF
0.5
×
VDDQ
Max
2.7
0
0.51
×
VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
Unit
V
V
V
V
V
V
V
2
3
4
Notes
1
0.5
×
VDDQ + 0.2V V
VDDQ + 0.6
V
5, 6
Notes: 1.VDDQ must be lower than or equal to VDD.
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
4. VIN (DC) specifies the allowable dc execution of each differential input.
5. VID (dc) specifies the input differential voltage required for switching.
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V
if measurement.
Preliminary Data Sheet E0295E20 (Ver. 2.0)
10