EBD11UD8ADDA-E
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Input capacitance
Input capacitance
Input capacitance
Data and DQS input/output
capacitance
Symbol
CI1
CI2
CI3
CO
Pins
Address, /RAS, /CAS, /WE
CK, /CK
CKE, /CS
DQ, DQS, DM
max.
90
70
60
30
Unit
pF
pF
pF
pF
Notes
1, 3
1, 3
1, 3
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
∆VOUT
= 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100%tested.
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
Parameter
Clock cycle time
(CL = 2)
(CL = 2.5)
CK high-level width
CK low-level width
CK half period
DQ output access time from
CK, /CK
DQS output access time from CK,
/CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data hold skew factor
Symbol min.
tCK
tCK
tCH
tCL
tHP
tAC
7.5
6
0.45
0.45
min
(tCH, tCL)
–0.7
max.
12
12
0.55
0.55
—
0.7
0.6
0.45
-7A
min.
7.5
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max.
12
12
0.55
0.55
—
0.75
0.75
0.5
-7B
min.
10
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
–0.75
—
max.
12
12
0.55
0.55
—
0.75
0.75
0.5
Unit
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
8
9
8
8
7
5, 11
6, 11
2, 11
2, 11
3
Notes
10
tDQSCK –0.6
tDQSQ
tQH
tQHS
—
tHP – tQHS —
—
–0.7
–0.7
0.9
0.4
0.45
0.45
1.75
0.55
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
tHP – tQHS —
—
–0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
tHP – tQHS —
—
–0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.75
1.1
0.6
—
—
—
—
—
0.6
1.25
—
—
—
—
—
Data-out high-impedance time from
tHZ
CK, /CK
Data-out low-impedance time from
tLZ
CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
Write postamble
Write command to first DQS
latching transition
tRPRE
tRPST
tDS
tDH
tDIPW
tWPRES 0
tWPRE
tWPST
tDQSS
0.25
0.4
0.75
0.2
0.2
0.35
0.35
0.75
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from CK tDSH
DQS input high pulse width
DQS input low pulse width
Address and control input setup
time
tDQSH
tDQSL
tIS
Data Sheet E0603E10 (Ver. 1.0)
12
ELPIDA [ ELPIDA MEMORY ]
