EBD11UD8ADDA-E
Block Diagram
/CS1
/CS0
RS
DQS0
RS
DM0
8
DQ0 to DQ7
RS
DQS1
RS
DM1
8
DQ8 to DQ15
RS
DM
DQS
/CS
DQS
DM
/CS
DQS5
RS
DM5
8
DQ40 to DQ47
RS
DM
RS
I/O0 to I/O7
I/O0 to I/O7
DQ32 to DQ39
RS
DQS
/CS
DQS /CS
DM
DM
DQS
RS
DQS4
RS
DM4
8
RS
I/O0 to I/O7
I/O0 to I/O7
DM
DQS
/CS
DQS
DM
/CS
/CS
DQS
DM
/CS
D0
D8
D4
D12
D1
D9
D5
D13
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
RS
I/O0 to I/O7
RS
DQS2
RS
DM2
8
DQ16 to DQ23
RS
DQS3
RS
DM3
8
DQ24 to DQ31
RS
DM
DQS
RS
DM
DQS
/CS
DQS
DM
/CS
DQS6
RS
DM6
8
DQ48 to DQ55
RS
DQS7
RS
DM7
8
DQ56 to DQ63
RS
RS
DQS
DM
/CS
DQS
DM
/CS
D2
/CS
D10
/CS
D6
/CS
D14
I/O0 to I/O7
I/O0 to I/O7
DQS
DM
I/O0 to I/O7
DQS
DM
I/O0 to I/O7
DQS /CS
DM
D3
D11
D7
D15
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
Serial PD
SCL
SA0
BA0 to BA1
A0 to AN
/RAS
/CAS
/WE
CKE0
CKE1
VDDSPD
VREF
VDD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D7)
SDRAMs (D8 to D15)
SPD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15), VDD and VDDQ
Notes :
VSS
VDDID
Open
* D0 to D15 : 512M bits DDR SDRAM
U0 : 2k bit EEPROM
Rs : 22
Ω
SDRAMs (D0 to D15), SPD
SDRAMs (D0 to D15), SPD
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
Strap in (closed): VDD
≠
VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
CK0
/CK0
CK1
/CK1
CK2
/CK2
8 loads
8 loads
10pF
SA2
SA1
SCL
A0
A1
A2
SDA
SDA
U0
WP
Data Sheet E0603E10 (Ver. 1.0)
8
ELPIDA [ ELPIDA MEMORY ]
