EBD25RB4ALFA
Byte No.
27
Function described
Minimum row precharge time (tRP)
(-7A)
(-75)
(-1A)
28
Minimum row active to row active
delay (tRRD)
(-7A)
(-75)
(-1A)
29
Minimum /RAS to /CAS delay (tRCD)
(-7A)
(-75)
(-1A)
30
Minimum active to precharge time
(tRAS)
(-7A)
(-75)
(-1A)
31
32
Module bank density
Address and command setup time
before clock (tIS)
(-7A)
(-75)
(-1A)
33
Bit7
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Bit6
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
Bit5 Bit4
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
0
Bit3
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Bit2
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Bit1 Bit0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Hex value
50H
50H
50H
3CH
3CH
3CH
50H
50H
50H
2DH
2DH
32H
40H
90H
90H
B0H
90H
90H
B0H
50H
50H
60H
50H
50H
60H
00H
00H
A2H
CDH
73H
FEH
00H
Elpida Memory
Comments
20ns
20ns
20ns
15ns
15ns
15ns
20ns
20ns
20ns
45ns
45ns
50ns
256Mbytes
0.9ns
0.9ns
1.1ns
0.9ns
0.9ns
1.1ns
0.5ns
0.5ns
0.6ns
0.5ns
0.5ns
0.6ns
Future Use
Address and command hold time after
1
clock (tIH)
(-7A)
(-75)
(-1A)
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
34
Data input setup time before clock
(tDS)
(-7A)
(-75)
(-1A)
35
Data input hold time after clock (tDH)
(-7A)
(-75)
(-1A)
36 to 61
62
63
Superset information
SPD Revision
Checksum for bytes 0 to 62
(-7A)
(-75)
(-1A)
64
65 to 71
72
73 to 90
91 to 92
93 to 94
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Manufacturer’s part number
Revision code
Manufacturing date
Preliminary Data Sheet E0211E11 (Ver. 1.1)
6
ELPIDA [ ELPIDA MEMORY ]
