EBD25RB4ALFA
Differential Clock Net Wiring (CLK0, /CLK0)
0ns (nominal)
SDRAM
stack
120Ω
PLL
OUT1
CLK0
120Ω
IN
SDRAM
stack
240Ω
Register1
/CLK0
120Ω
C
OUT'N'
(Typically two registers per DIMM)
Feedback
240Ω
Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl
be set to 0ns (nominal).
2. Input, output and feedback clock lines are terminated from line to line as shown, and not
from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired
in a similar manner.
4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Preliminary Data Sheet E0211E11 (Ver. 1.1)
8
ELPIDA [ ELPIDA MEMORY ]
