EBD52UD6ADSA-E
Byte No. Function described
29
Minimum /RAS to /CAS delay (tRCD)
-6B
-7A, -7B
30
Minimum active to precharge time
(tRAS)
-6B
-7A, -7B
31
32
Module rank density
Address and command setup time
before clock (tIS)
-6B
-7A, -7B
33
Address and command hold time after
clock (tIH)
-6B
-7A, -7B
34
Bit7
0
0
0
0
0
0
1
0
1
Bit6
1
1
0
0
1
1
0
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
1
1
1
0
Bit5
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
0
0
1
1
1
0
Bit4
0
1
0
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
1
1
0
Bit3
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
1
1
1
0
Bit2
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
Bit1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
Bit0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
0
0
Hex value
48H
50H
2AH
2DH
40H
75H
90H
75H
90H
45H
50H
45H
50H
00H
3CH
41H
48H
4BH
30H
2DH
32H
55H
75H
00H
00H
09H
C0H
EBH
7FH
FEH
00H
Continuation
code
Elpida Memory
(ASCII-8bit
code)
E
B
Comments
18ns
20ns
42ns
45ns
256M bytes
×
2 ranks
0.75ns
0.9ns
*1
*1
0.75ns
0.9ns
*1
*1
Data input setup time before clock (tDS)
0
-6B
-7A, -7B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
Data input hold time after clock (tDH)
-6B
-7A, -7B
Superset information
Active command period (tRC)
-6B
-7A, -7B
Auto refresh to active/
Auto refresh command cycle (tRFC)
-6B
-7A, -7B
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-6B
-7A, -7B
Data hold skew (tQHS)
-6B
-7A, -7B
Superset information
SPD Revision
Checksum for bytes 0 to 62
-6B
-7A
-7B
0.45ns
0.5ns
*1
*1
35
0.45ns
0.5ns
*1
*1
36 to 40
41
Future use
60ns
65ns
72ns
75ns
*1
*1
42
*1
*1
1
43
44
12ns*
0.45ns
0.5ns
*1
*1
45
0.55ns
0.75ns
*1
*1
46 to 61
62
63
Future use
64 to 65
66
67 to 71
72
73
74
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Module part number
Module part number
×
0
0
×
1
1
×
0
0
×
0
0
×
0
0
×
1
0
×
0
1
×
1
0
××
45H
42H
Data Sheet E0604E10 (Ver. 1.0)
6
ELPIDA [ ELPIDA MEMORY ]
