EBD52UD6ADSA-E
Block Diagram
/CS1
/CS0
RS
RS
DQS0
RS
LDQS
LDM
/CS
LDQS
LDM
/CS
DQS4
RS
LDQS
LDM
/CS
LDQS
LDM
/CS
DM0
8
RS
DM4
8
RS
DQ0 to DQ7
RS
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
DQ32 to DQ39
RS
I/O0 to I/O7
UDQS
RS
UDM
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
DQS1
RS
D0
D4
DQS5
D2
D6
DM1
8
RS
DM5
8
RS
DQ8 to DQ15
DQ40 to DQ47
I/O8 to I/O15
RS
RS
DQS2
RS
LDQS
LDM
/CS
LDQS
LDM
/CS
DQS6
RS
LDQS
LDM
/CS
LDQS
LDM
/CS
DM2
8
RS
DM6
8
RS
DQ16 to DQ23
RS
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
DQ48 to DQ55
RS
I/O0 to I/O7
UDQS
RS
UDM
I/O0 to I/O7
UDQS
UDM
I/O8 to I/O15
DQS3
RS
D1
D5
DQS7
D3
D7
DM3
8
RS
DM7
8
RS
DQ24 to DQ31
DQ56 to DQ63
I/O8 to I/O15
* D0 to D7 : 512M bits DDR SDRAM
U0 : 2k bits EEPROM
Rs : 22
Ω
BA0 to BA1
A0 to AN
/RAS
/CAS
/WE
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
Serial PD
SCL
SA0
SA1
SA2
SCL
SDA
SDA
A0
A1
A2
U0
CKE0
CKE1
VDDSPD
VREF
VDD
SDRAMs (D0 to D3)
SDRAMs (D4 to D7)
SPD
SDRAMs (D0 to D7)
SDRAMs (D0 to D7),
VDD
and
VDDQ
CK0
/CK0
CK1
/CK1
CK2
WP
4 loads
4 loads
10 pF
VSS
VDDID
Open
SDRAMs (D0 to D7), SPD
/CK2
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
Strap in (closed): VDD
≠
VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Data Sheet E0604E10 (Ver. 1.0)
8
ELPIDA [ ELPIDA MEMORY ]
