EBE21UE8AFSA
Byte No.
26
Function described
Maximum data access time (tAC)
from clock at CL = X
−
2
-8G (CL = 4)
-6E (CL = 3)
Bit7
0
0
0
0
Bit6
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Bit5
0
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
Bit4
1
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
1
0
0
Bit3
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
Bit2
0
0
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
1
1
1
0
1
0
1
0
0
Bit1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
0
0
0
1
1
0
Bit0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
Hex value Comments
50H
60H
3CH
1EH
3CH
2DH
01H
17H
20H
25H
27H
05H
10H
12H
17H
3CH
1EH
1EH
00H
06H
3CH
7FH
80H
14H
18H
1EH
22H
00H
60ns*
1
0.5ns*
0.6ns*
15ns
7.5ns
15ns
45ns
1
1
27
28
29
30
31
32
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
Minimum active to precharge time
(tRAS)
Module rank density
Address and command setup time
before clock (tIS)
-8G
-6E
Address and command hold time
after clock (tIH)
-8G
-6E
Data input setup time before clock
(tDS)
-8G
-6E
Minimum /RAS to /CAS delay (tRCD) 0
0
0
0
0
0
0
0
0
1G bytes
0.17ns*
0.20ns*
0.25ns*
0.27ns*
0.05ns*
0.10ns*
0.12ns*
0.17ns*
15ns*
1
1
1
33
1
1
34
1
1
35
Data input hold time after clock (tDH)
0
-8G
-6E
0
0
1
1
36
37
38
39
40
41
42
43
44
Write recovery time (tWR)
Internal write to read command delay
0
(tWTR)
Internal read to precharge command
0
delay (tRTP)
Memory analysis probe
0
characteristics
Extension of Byte 41 and 42
Active command period (tRC)
Auto refresh to active/
Auto refresh command cycle (tRFC)
SDRAM tCK cycle max. (tCK max.)
Dout to DQS skew
-8G
-6E
Data hold skew (tQHS)
-8G
-6E
0
0
0
1
0
0
0
0
0
7.5ns*
7.5ns*
TBD
1
1
127.5ns*
8ns*
1
1
0.20ns*
0.24ns*
0.30ns*
0.34ns*
1
1
45
1
1
46
PLL relock time
Undefined
Data Sheet E1459E20 (Ver. 2.0)
6
ELPIDA [ ELPIDA MEMORY ]
