EBJ21UE8BFU0
Serial PD Matrix
-DJ
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Function described
Number of serial PD bytes written/
SPD device size/CRC coverage
SPD revision
Key byte/DRAM device type
Key byte/module type
SDRAM density and banks
SDRAM addressing
Module nominal voltage, VDD
Module organization
Module memory bus width
Fine timebase (FTB)
dividend/divisor
Medium timebase (MTB) dividend
Medium timebase (MTB) divisor
SDRAM minimum cycle time
(tCK (min.))
Reserved
SDRAM CAS latencies supported,
MSB
SDRAM minimum CAS latencies
time (tAA (min.))
SDRAM minimum write recovery
time (tWR (min.))
SDRAM minimum /RAS to /CAS
delay (tRCD (min.))
SDRAM minimum row active to row
active delay (tRRD (min.))
SDRAM minimum row precharge
time (tRP (min.))
SDRAM upper nibbles for tRAS and
tRC
SDRAM minimum active to
precharge time (tRAS (min.)), LSB
SDRAM minimum active to active
/auto-refresh time (tRC (min.)), LSB
SDRAM minimum refresh recovery
time delay (tRFC (min.)), LSB
SDRAM minimum refresh recovery
time delay (tRFC (min.)), MSB
SDRAM minimum internal write to
read command delay (tWTR (min.))
SDRAM minimum internal read to
precharge command delay
(tRTP (min.))
Upper nibble for tFAW
Minimum four activate window delay
time (tFAW (min.))
SDRAM optional features
SDRAM thermal and refresh options
Hex Comments
92h 176/256/0-116
10h Rev.1.0
0Bh DDR3 SDRAM
03h SO-DIMM
02h 1G bits, 8 banks
11h
14 rows,
10 columns
-GN
Hex Comments
92h 176/256/0-116
10h Rev.1.0
0Bh DDR3 SDRAM
03h SO-DIMM
02h 1G bits, 8 banks
11h
14 rows,
10 columns
-GL
Hex Comments
92h 176/256/0-116
10h Rev.1.0
0Bh DDR3 SDRAM
03h SO-DIMM
02h 1G bits, 8 banks
11h
14 rows,
10 columns
00h 1.5V
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
52h 5/2
01h 1
08h 8
0Ch 1.5ns
00h —
00h 1.5V
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
52h 5/2
01h 1
08h 8
0Ah 1.25ns
00h —
FEh 5, 6, 7, 8, 9, 10, 11
00h —
69h 13.125ns
78h 15ns
69h 13.125ns
30h 6ns
69h 13.125ns
11h —
18h 35ns
81h 48.125ns
70h 110ns
03h 110ns
3Ch 7.5ns
3Ch 7.5ns
00h 30ns
F0h 30ns
83h DLL-off, RZQ/6, 7
00h 1.5V
09h 2 ranks/×8 bits
03h 64 bits/non-ECC
52h 5/2
01h 1
08h 8
0Ah 1.25ns
00h —
FEh 5, 6, 7, 8, 9, 10, 11
00h —
64h 12.5ns
78h 15ns
64h 12.5ns
30h 6ns
64h 12.5ns
11h —
18h 35ns
7Ch 47.5ns
70h 110ns
03h 110ns
3Ch 7.5ns
3Ch 7.5ns
00h 30ns
F0h 30ns
83h DLL-off, RZQ/6, 7
SDRAM CAS latencies supported, LSB7Eh 5, 6, 7, 8, 9, 10
00h —
69h 13.125ns
78h 15ns
69h 13.125ns
30h 6ns
69h 13.125ns
11h —
20h 36ns
89h 49.125ns
70h 110ns
03h 110ns
3Ch 7.5ns
3Ch 7.5ns
00h 30ns
F0h 30ns
83h DLL-off, RZQ/6, 7
81h
PASR/2X refresh at
PASR/2X refresh at
PASR/2X refresh at
81h
81h
+85ºC to +95ºC
+85ºC to +95ºC
+85ºC to +95ºC
Data Sheet E1642E30 (Ver. 3.0)
5
ELPIDA [ ELPIDA MEMORY ]
