EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
1. Input/Output Pin Function
Pin name
CLK, /CLK
Input/Output
Input
Function
CLK and /CLK are the master clock inputs. The timing reference point for the differential
clock is when CLK and /CLK cross.
All control and address inputs except for DQ and DM are latched by a rising edge of CLK.
By both of rising and falling edges of CLK, output DQ and DQS are validated.
CKE
Input
CKE controls power down mode. When the EDD12xxALTA is not in burst mode and CKE
is negated, the device enters power down mode and deactivates internal clock signals,
input buffers and output drivers. During power down mode, CKE must remain low.
/CS low starts a command input cycle. When /CS is high, commands are ignored but the
current operations will be continued.
As well as regular SDRAMs, each combination of /RAS, /CAS, and /WE input in
conjunction with /CS input at a rising edge of CLK determines SDRAM operation. Refer to
the command table.
Row address is determined by A0 - A11 at the rising edge of CLK in active command
cycle.
It does not depend on the bit organization.
Column address is determined by A0 - A9, A11 at the rising edge of CLK in read or write
command cycle. It depends on the bit organization: A0 - A9, A11 for x4 device, A0 - A9
for x8 device, A0 - A8 for x16 device.
A10 defines precharge mode. When A10 is high in precharge command cycle, all banks
are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, precharge starts automatically after the
burst access.
/CS
/RAS, /CAS,
/WE
A0 – A11
Input
Input
Input
BA0, BA1
Input
BA0, BA1 are bank select signals. In command cycle, BA0 and BA1 low select Bank A,
BA0 high and BA1 low select bank B, BA0 low and BA1 high select bank C and then BA0
and BA1 high select bank D.
DQ pins have the same function as I/O pins on conventional DRAMs.
Active on the both edges for data input and output.
DM's are latched by both of rising and falling edges of the DQS. In write mode, DM's
control byte mask. Unlike regular SDRAMs, DM's do not control read operation.
V
REF
is reference voltage for SSTL input buffers.
DQ0 – DQ15
DQS, LDQS,
UDQS
DM, LDM, UDM
V
REF
V
DD
, V
DD
Q, V
SS
,
V
SS
Q
Input/Output
Input/Output
Input
Input
(Power Supply) V
DD
and V
SS
are power supply pins for internal circuits. V
DD
Q and V
SS
Q are power supply
pins for the output buffers.
10
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
