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EDD1232ACBH-5B-F 参数 Datasheet PDF下载

EDD1232ACBH-5B-F图片预览
型号: EDD1232ACBH-5B-F
PDF下载: 下载PDF文件 查看货源
内容描述: 128M比特DDR SDRAM [128M bits DDR SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 51 页 / 633 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD1232ACBH  
Row address strobe and bank activate [ACT]  
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX11).  
(See Bank Select Signal Table)  
Precharge selected bank [PRE]  
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)  
[Bank Select Signal Table]  
BA0  
L
BA1  
L
Bank 0  
Bank 1  
H
L
Bank 2  
L
H
Bank 3  
H
H
Remark: H: VIH. L: VIL.  
Precharge all banks [PALL]  
This command starts a precharge operation for all banks.  
Refresh [REF/SELF]  
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another  
is self-refresh. For details, refer to the CKE truth table section.  
Mode register set/Extended mode register set [MRS/EMRS]  
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it  
works. The both mode registers are set through the address pins (the A0 to the A11, BA0 to BA1) in the mode  
register set cycle. For details, refer to "Mode register and extended mode register set".  
CKE Truth Table  
CKE  
Current state  
Command  
n – 1  
H
n
/CS  
L
/RAS /CAS /WE  
Address  
Notes  
Idle  
Idle  
Idle  
Auto-refresh command (REF)  
Self-refresh entry (SELF)  
Power down entry (PDEN)  
H
L
L
L
H
H
H
×
×
×
×
×
×
×
×
×
2
2
H
L
L
L
H
L
L
H
×
H
×
H
L
H
L
Self refresh  
Power down  
Self refresh exit (SELFX)  
Power down exit (PDEX)  
L
H
H
H
H
H
×
H
×
H
×
L
H
L
L
H
×
H
×
H
×
L
H
Remark: H: VIH. L: VIL. ×: VIH or VIL.  
Notes: 1. All the banks must be in IDLE before executing this command.  
2. The CKE level must be kept for 1 CK cycle at least.  
Data Sheet E1202E20 (Ver.2.0)  
15