EDD1232ACBH
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V
−0.125V/+0.2V)
Parameter
Input capacitance
Symbol
CI1
CI2
Data input/output capacitance
CI/O
Pins
CK, /CK
All other input pins
DQ, DM, DQS
min.
1
1
1
typ.
—
—
—
max.
5
4
6
Unit
pF
pF
pF
Notes
1
1
1, 2
Notes: 1. These parameters are measured on conditions:
TA = +25°C.
2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2,
∆VOUT
= 0.2V,
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V
−0.125V/+0.2V,
VSS, VSSQ = 0V)
-5B
Parameter
Clock cycle time
CK high-level width
CK low-level width
CK half period
DQ output access time from
CK, /CK
DQS output access time from
CK, /CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time
from CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble hold time
Write postamble
Write command to first DQS latching transition
166MHz < Operating frequency
≤
200MHz
Operating frequency
≤
166MHz
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
166MHz < Operating frequency
≤
200MHz
Operating frequency
≤
166MHz
DQS input low pulse width
166MHz < Operating frequency
≤
200MHz
Operating frequency
≤
166MHz
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Symbol
tCK
tCH
tCL
tHP
tAC
tDQSCK
tDQSQ
tQH
tHZ
tLZ
tRPRE
tRPST
tDS
tDH
tDIPW
tWPRES
tWPREH
tWPST
tDQSS
tDQSS
tDSS
tDSH
tDQSH
tDQSH
tDQSL
tDQSL
tIS
tIH
tIPW
min.
5
0.45
0.45
min
(tCH, tCL)
–0.7
–0.7
—
tHP – 0.45
—
–0.7
0.9
0.4
0.45
0.45
1.75
0
0.25
0.4
0.8
0.75
0.2
0.2
0.4
0.35
0.4
0.35
1.0
1.0
2.2
max.
12
0.55
0.55
—
0.7
0.7
0.45
—
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.2
1.25
—
—
—
—
—
—
—
—
—
Unit
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
8
8
7
9
8
8
7
5, 11
6, 11
2, 11
2, 11
3
Notes
10
Data Sheet E1202E20 (Ver.2.0)
7
ELPIDA [ ELPIDA MEMORY ]
