EDD5108AGTA-4, EDD5116AGTA-4
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)
Parameter
Input capacitance
Symbol
CI1
CI2
Delta input capacitance
Cdi1
Cdi2
Data input/output capacitance
Delta input/output capacitance
CI/O
Cdio
Pins
CK, /CK
All other input pins
CK, /CK
All other input-only pins
DQ, DM, DQS
DQ, DM, DQS
min.
2.0
2.0
—
—
4.0
—
typ.
—
—
—
—
—
—
max.
3.0
3.0
0.25
0.5
5
0.5
Unit
pF
pF
pF
pF
pF
pF
Notes
1
1
1
1
1, 2
1
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2,
ΔVOUT
= 0.2V.
2. DOUT circuits are disabled.
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)
-4B
Parameter
Clock cycle time
CK high-level width
CK low-level width
CK half period
DQ output access time from CK, /CK
DQS output access time from CK, /CK
DQS to DQ skew
DQ/DQS output hold time from DQS
Data hold skew factor
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time
from CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
Write postamble
Symbol
tCK
tCH
tCL
tHP
tAC
tDQSCK
tDQSQ
tQH
tQHS
tHZ
tLZ
tRPRE
tRPST
tDS
tDH
tDIPW
tWPRES
tWPRE
tWPST
min.
4
0.45
0.45
min
(tCH, tCL)
–0.7
–0.55
—
max.
8
0.55
0.55
—
0.7
0.55
0.4
-4C
min.
4
0.45
0.45
min
(tCH, tCL)
–0.7
–0.55
—
max.
8
0.55
0.55
—
0.7
0.55
0.4
Unit
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
tCK
8
8
7
9
8
8
7
5, 11
6, 11
2, 11
2, 11
3
Notes
10
tHP – tQHS —
—
—
–0.7
0.9
0.4
0.4
0.4
1.75
0
0.3
0.4
0.85
0.3
0.3
0.4
0.4
0.6
0.6
2.2
3
0.5
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.15
—
—
—
—
—
—
—
—
tHP – tQHS —
—
—
–0.7
0.9
0.4
0.4
0.4
1.75
0
0.3
0.4
0.85
0.3
0.3
0.4
0.4
0.6
0.6
2.2
3
0.5
0.7
0.7
1.1
0.6
—
—
—
—
—
0.6
1.15
—
—
—
—
—
—
—
—
Write command to first DQS latching transition tDQSS
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
DQS input low pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIPW
tMRD
Data Sheet E1195E20 (Ver. 2.0)
7
ELPIDA [ ELPIDA MEMORY ]
