EDJ1104BFBG, EDJ1108BFBG
Single-Ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain
requirements for single-ended signals.
CK and /CK have to approximately reach VSEH min. / VSEL max. (approximately equal to the AC-levels (VIH(AC) /
VIL(AC)) for Address/command signals) in every half-cycle.
DQS, /DQS have to reach VSEH min./VSEL max. (approximately the AC-levels (VIH(AC) / VIL(AC)) for DQ signals)
in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for Address/command and DQ’s might be different per speed-bin etc. E.g. if VIH
150 (AC)/VIL 150 (AC) is used for Address/command signals, then these ac-levels apply also for the single ended
components of differential CK and /CK.
Single-Ended Requirement for Differential Signals.
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components
of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but adds a restriction
on the common mode characteristics of these signals.
Preliminary Data Sheet E1629E20 (Ver. 2.0)
17
ELPIDA [ ELPIDA MEMORY ]
