EDJ1104BFBG, EDJ1108BFBG
Input Slew Rate Derating
For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data
sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the
∆tIS, ∆tDS
and
∆tIH, ∆tDH
derating value
respectively.
Example: tDS (total setup time) = tDS (base) +
∆tDS.
Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF
(DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is
always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for
derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the
slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure
of Slew Rate Definition Tangent).
Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal
is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew
rate for derating value (See the figure of Slew Rate Definition Nominal).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’,
the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value
(see the figure of Slew Rate Definition Tangent).
For a valid transition the input signal has to remain above/below VIH/VIL(AC) for some time tVAC (see the table of
Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL (AC).
For slew rates in between the values listed in the tables below, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[Address/Command Setup and Hold Base-Values for 1V/ns]
DDR3-1066
tIS(base) AC175
tIH(base) DC100
tIS(base) AC150
125
200
125 + 150
DDR3-1333
65
140
65 + 125
DDR3-1600
45
120
45 + 125
Unit
ps
ps
ps
Reference
VIH/VIL(AC)
VIH/VIL(DC)
VIH/VIL(AC)
Notes: 1. AC/DC referenced for 1V/ns Address/Command slew rate and 2V/ns differential CK, /CK slew rate.
2. The tHS (base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional
100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to
account for the earlier reference point [(175mV
−
150mV)/1V/ns]
Preliminary Data Sheet E1629E20 (Ver. 2.0)
9
ELPIDA [ ELPIDA MEMORY ]
