EDJ1104BFSE, EDJ1108BFSE
Pin Configurations
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
1
A
VSS
B
VSS VSSQ
C
VDDQ
D
VSSQ
E
VREFDQ VDDQ
F
NC
G
ODT
H
NC
J
VSS
K
VDD
L
VSS
M
N
VSS /RESET A13
(Top view)
NC
A8
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
M
N
VSS /RESET A13
(Top view)
NC
A8
VSS
A3
A0
A12(/BC) BA1
VDD
L
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
BA0
BA2
NC
VREFCA VSS
K
VDD
A3
A0
A12(/BC) BA1
VDD
/CS
/WE
A10(AP)
ZQ
NC
J
VSS
BA0
BA2
NC
VREFCA VSS
VDD
/CAS
/CK
VDD
CKE
H
NC
/CS
/WE
A10(AP)
ZQ
NC
VSS
/RAS
CK
VSS
NC
G
ODT
VDD
/CAS
/CK
VDD
CKE
NC
NC
NC
VDDQ
F
NC
VSS
/RAS
CK
VSS
NC
NC
/DQS
VDD
VSS
VSSQ
E
VREFDQ VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
D
VSSQ
DQ6
/DQS
DQ4
VDD
DQ7
VSS
DQ5
VSSQ
VDDQ
DQ0
DM
VSSQ VDDQ
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
VDD
NC
NC
VSS
VDD
B
VSS VSSQ
DQ0
DM/TDQS
VSSQ VDDQ
78-ball FBGA (×8 configuration)
9
A
VSS
VDD
NC
NU/(/TDQS)
VSS
2
3
7
8
1
2
3
7
8
9
VDD
Pin name
A0 to A13*
3
Function
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
3
Pin name
/RESET*
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
NU*
1
2
3
Function
Active low asynchronous reset
Supply voltage for internal
circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Reference pin for ZQ
calibration
No connection
Not usable
BA0 to BA2*
DQ0 to DQ7
DQS, /DQS
Bank select
Data input/output
Differential data strobe
Termination data strobe
Chip select
3
TDQS, /TDQS
/CS*
3
/RAS, /CAS, /WE*
CKE*
3
Command input
Clock enable
Differential clock input
Write data mask
CK, /CK
DM
ODT*
3
ODT control
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E1653E20 (Ver. 2.0)
3
ELPIDA [ ELPIDA MEMORY ]
