EDL5132CBMA
Synchronous Characteristics
Parameter
Clock cycle time
(CL= 2)
(CL= 3)
Access time from CLK
(CL= 2)
(CL= 3)
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time
(CL= 2)
(CL= 3)
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
CKE setup time (Power down exit)
Command (/CS, /RAS, /CAS, /WE,
DQM) setup time
Command (/CS, /RAS, /CAS, /WE,
DQM) hold time
Symbol
tCK2
tCK3
tAC2
tAC3
tCH
tCL
tOH
tLZ
tHZ2
tHZ3
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
tCMH
min.
15
10
—
—
3
3
3
0
3
3
2
1
2
1
2
1
2
2
1
max.
—
—
9
7
—
—
—
—
9
7
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
Note
Note: 1. Output load.
Z = 50
Ω
Output
30 pF
Output load
Preliminary Data Sheet E0490E30 (Ver. 3.0)
8
ELPIDA [ ELPIDA MEMORY ]
