EDS2504APTA/08APTA/16APTA-TI
DC Characteristics 1 (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
°
Parameter
/CAS latency
Operating current
Symbol
ICC1
ICC1
Standby current in power
down
Standby current in power
down (input signal stable)
Standby current in non
power down
Standby current in non
power down (input signal
stable)
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in
non power down
Active standby current in
non power down (input
signal stable)
Burst operating current
Refresh current
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
ICC5
Self refresh current
ICC6
-7A
-75
Grade
-7A
-75
max.
×
4
130
110
3
2
20
9
4
3
30
15
130
250
220
3
×
8
130
110
3
2
20
9
4
3
30
15
135
250
220
3
×
16
135
115
3
2
20
9
4
3
30
15
145
250
220
3
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
Burst length = 1
tRC = min.
Burst length = 1
tRC = min.
CKE = VIL, tCK = min.
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = min.
CKE = VIH, tCK =
∞,
/CS = VIH
CKE = VIL, tCK = min.
CKE = VIL, tCK =
∞
CKE, /CS = VIH,
tCK = min.
CKE = VIH, tCK =
∞,
/CS = VIH
tCK = min., BL = 4
tRC = min.
tRC = min.
VIH
≥
VDD
– 0.2V
VIL
≤
0.2V
Notes
1, 2, 3
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
5