EDS2504APTA/08APTA/16APTA-TI
Test Conditions
•
Input and output timing reference levels: 1.4V
•
Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V
0.8 V
I/O
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
Frequency (MHz)
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3)
Column command to column command
Write command to data in latency
DQM to data in
DQM to data out
CKE to CLK disable
Register set to active command
/CS to command disable
Power down exit to command input
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
lSEC
lHZP
lHZP
lAPR
lEP
lEP
lCCD
lWCD
lDID
lDOD
lCLE
lMRD
lCDD
lPEC
-7A
133
7.5
2
8
6
2
2
2
1
4
8
2
3
1
–1
–2
1
0
0
2
1
2
0
1
7.5
3
9
6
3
2
2
1
5
9
2
3
1
–1
–2
1
0
0
2
1
2
0
1
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
-75
Notes: 1.IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Preliminary Data Sheet E0248E10 (Ver. 1.0)
7
ELPIDA [ ELPIDA MEMORY ]
