EDS2532EEBH-9A
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-9A
Parameter
System clock cycle time
(CL = 2)
(CL = 3)
CLK high pulse width
CLK low pulse width
Access time from CLK
Data-out hold time
CLK to Data-out low impedance
CLK to Data-out high impedance
Input setup time
Input hold time
Ref/Active to Ref/Active command period
Active to Precharge command period
Active command to column command (same bank)
Precharge to active command period
Write recovery or data-in to precharge lead time
Last data into active latency
Active (a) to Active (b) command period
Transition time (rise and fall)
Refresh period
(4096 refresh cycles)
Symbol
tCK
tCK
tCH
tCL
tAC
tOH
tLZ
tHZ
tSI
tHI
tRC
tRAS
tRCD
tRP
tDPL
tDAL
tRRD
tT
tREF
min.
9
9
3
3
—
2.5
0
—
2
1
68
50
18
18
18
2CLK + 18ns
18
0.5
—
max.
—
—
—
—
7
—
—
7
—
—
—
120000
—
—
—
—
—
1.0
64
ns
ns
ms
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1, 5
1, 5
1, 2, 5, 6
1, 2, 5, 6
1, 2, 3, 5, 6
1, 4, 6
1, 5
1, 5
1
1
1
1
1
Notes: 1.
2.
3.
4.
5.
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 0.5
×
VDDQ.
Access time is measured at 0.5
×
VDDQ. Load condition is CL = 30pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
If tT
≥
1ns, each parameters is changed as follows;
tAC, tOH, tLZ: should be added (tT (rise)/2 – 0.5)
tCH, tCL, tSI, tHI: should be added {(tT (rise) + tT (fall))/2 – 1}
6. Driver strength is Half condition.
Preliminary Data Sheet E0617E40 (Ver. 4.0)
7
ELPIDA [ ELPIDA MEMORY ]
