EDS2532EGBH-TT
DC Characteristics 1 (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Operating current
Symbol
IDD1
Grade
-6D
-7B
max.
50
50
0.8
0.6
10
4.0
4.0
3.0
15
10
-6D
-7B
-6D
-7B
85
70
110
100
3.0
Unit
mA
Test condition
Burst length = 1
tRC = tRC (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
0.3V,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
0.3V, tCK =
∞
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE, /CS = VIH,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE = VIH, tCK =
∞,
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
VIL,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE
≤
VIL, tCK =
∞
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE, /CS = VIH,
tCK = tCK (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
CKE = VIH, tCK =
∞,
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
tCK = tCK (min.),
BL = 4
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
tRC = tRC (min.)
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
VIL
≤
0.3V, VIH
≥
0.8V
×
VDD
Notes
1, 2, 3
Standby current in power down
Standby current in power down
(input signal stable)
Standby current in non power down
Standby current in non power down
(input signal stable)
Active standby current in power down
Active standby current in power down
(input signal stable)
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
6
7
4
8
1, 2, 6
2, 7
1, 2, 4
2, 8
1, 2, 5
3
Active standby current in non power down IDD3N
Active standby current in non power down
IDD3NS
(input signal stable)
Burst operating current
Refresh current
Self-refresh current
IDD4
IDD5
IDD6
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E1200E40 (Ver. 4.0)
5
ELPIDA [ ELPIDA MEMORY ]
