EDS2532EGBH-TT
Test Conditions
•
Input and output timing reference levels: VDDQ
×
0.5
•
Input waveform and output load: See following figures
1.6V
input
0.2V
1.4V
0.3V
I/O
CL
t
T
tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge command
(same bank)
Active command to active command
(different bank)
Self-refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self-refresh exit to command input
Precharge command to high impedance
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
Column command to column command
Write command to data in latency
DQM to data in
DQM to data out
CKE to CLK disable
Mode register set to active command
/CS to command disable
Power down exit to command input
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
lSEC
lHZP
lAPR
lEP
lCCD
lWCD
lDID
lDOD
lCLE
lMRD
lCDD
lPEC
Number of clock cycle
6
3
10
7
3
3
2
1
6
11
3
1
–2
1
0
0
2
1
2
0
1
7.5
3
9
6
3
2
2
1
5
9
3
1
–2
1
0
0
2
1
2
0
1
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
= [lRC]
3
Notes
1
1
1
1
1
1
2
Notes: 1.
lRCD
to
lRRD
are recommended value.
2. Be valid [DESL] or [NOP] at next command of Self-refresh exit.
3. Except [DESL] and [NOP]
Preliminary Data Sheet E1200E40 (Ver. 4.0)
8
ELPIDA [ ELPIDA MEMORY ]
