HM5117805 Series
20. Data output turns off and becomes high impedance fromlater rising edge ofRAS and CAS . Hold
time and turn off time are specified by the timing specifications of laterrising edge of RAS andCAS
between tOHR and tOH and between tOFR and tOFF
.
21. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. Duringthis period, thedevice is in transition
state from normaloperation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS precharge time
should use tRPS instead of tRP.
22. If you use RAS only refresh or CBR burst refresh modein normalread/writecycles, 2048 cycles of
distributed CBR refresh with 15.6 µs interval should be executed within 32 ms immediately after
exiting from and before entering into the self refresh mode.
23. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering into
self refresh mode.
24. Repetitive self refresh mode without refreshing all memory is not allowed. Onceyouexit fromself
fresh mode, all memory cells need to be refreshed before re-enteringtheself refresh modeagain.
25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms,theirpinsmustbe
applied VIH or VIL.
Data Sheet E0156H10
13
ELPIDA [ ELPIDA MEMORY ]
