HM5164165F Series, HM5165165F Series
Operation Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
LCAS
×
L
H
UCAS WE
×
H
L
×
H
H
H
L*
2
L*
2
L*
2
L*
2
L*
2
L*
2
OE
×
L
L
L
×
×
×
H
H
H
I/O 0 to I/O 7
High-Z
Dout
High-Z
Dout
Din
×
Din
Din
×
Din
Dout/Din
High-Z
Dout/Din
High-Z
High-Z
High-Z
High-Z
I/O 8 to I/O 15 Operation
High-Z
High-Z
Dout
Dout
×
Din
Din
×
Din
Din
High-Z
Dout/Din
Dout/Din
High-Z
High-Z
High-Z
High-Z
RAS-only
refresh cycle
CAS-before-RAS
refresh cycle or
Self refresh cycle (L-version)
Read-modify-write cycle
Delayed write cycle
Early write cycle
Standby
Read cycle
EO
L
L
L
H
L
L
H
L
L
H
L
L
H
L
L
H
L
H
H
L
L
L
H
L
L
H
L
H
L
L
Notes: 1. H: V
IH
(inactive) L: V
IL
(active)
×:
V
IH
or V
IL
2. t
WCS
≥
0 ns: Early write cycle
t
WCS
< 0 ns: Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS.
(Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.) However write
operation and output High-Z control are done independently by each
UCAS, LCAS.
ex. if
RAS
= H to L,
LCAS
= L,
UCAS
= H, then
CAS-before-RAS
refresh cycle is selected.
L
H to L
H to L
H to L
×
H
H
H
H
×
×
×
×
H
L to H
L to H
L to H
od
Pr
High-Z
High-Z
Data Sheet E0099H10
Read cycle (Output disabled)
t
uc
7
ELPIDA [ ELPIDA MEMORY ]
