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HM5164805FLJ-5 参数 Datasheet PDF下载

HM5164805FLJ-5图片预览
型号: HM5164805FLJ-5
PDF下载: 下载PDF文件 查看货源
内容描述: 64男EDO DRAM ( 8 Mword × 8位)为8K刷新/ 4K的刷新 [64 M EDO DRAM (8-Mword × 8-bit) 8 k Refresh/4 k Refresh]
分类和应用: 存储内存集成电路光电二极管动态存储器
文件页数/大小: 34 页 / 220 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号HM5164805FLJ-5的Datasheet PDF文件第4页浏览型号HM5164805FLJ-5的Datasheet PDF文件第5页浏览型号HM5164805FLJ-5的Datasheet PDF文件第6页浏览型号HM5164805FLJ-5的Datasheet PDF文件第7页浏览型号HM5164805FLJ-5的Datasheet PDF文件第9页浏览型号HM5164805FLJ-5的Datasheet PDF文件第10页浏览型号HM5164805FLJ-5的Datasheet PDF文件第11页浏览型号HM5164805FLJ-5的Datasheet PDF文件第12页  
HM5164805F Series, HM5165805F Series  
DC Characteristics (HM5164805F Series)  
HM5164805F  
-5  
-6  
Parameter  
Operating current*1, *2  
Symbol Min  
Max  
115  
2
Min  
Max  
105  
2
Unit Test conditions  
ICC1  
ICC2  
mA  
mA  
tRC = min  
Standby current  
TTL interface  
RAS, CAS = VIH  
Dout = High-Z  
0.5  
0.5  
mA  
µA  
CMOS interface  
RAS, CAS VCC 0.2 V  
Dout = High-Z  
Standby current  
(L-version)  
ICC2  
300  
300  
CMOS interface  
RAS, CAS VCC 0.2 V  
Dout = High-Z  
RAS-only refresh current*2  
Standby current*1  
ICC3  
ICC5  
115  
5
105  
5
mA  
mA  
tRC = min  
RAS = VIH, CAS = VIL  
Dout = enable  
CAS-before-RAS refresh  
ICC6  
ICC7  
ICC10  
115  
110  
1.2  
105  
100  
1.2  
mA  
mA  
mA  
tRC = min  
current  
EDO page mode current*1, *3  
RAS = VIL , CAS cycle,  
tHPC = tHPC min  
Battery backup current*4  
(Standby with CBR refresh)  
(L-version)  
CMOS interface  
Dout = High-Z  
CBR refresh: tRC = 15.6µs  
tRAS 0.3 µs  
Self refresh mode current  
(L-version)  
ICC11  
500  
500  
µA  
CMOS interface  
RAS, CAS 0.2 V  
Dout = High-Z  
Input leakage current  
Output leakage current  
ILI  
5  
5  
5
5
5  
5  
5
5
µA  
µA  
0 V Vin VCC + 0.3 V  
ILO  
0 V Vout VCC  
Dout = disable  
Output high voltage  
Output low voltage  
VOH  
VOL  
2.4  
0
VCC  
0.4  
2.4  
0
VCC  
0.4  
V
V
High Iout = 2 mA  
Low Iout = 2 mA  
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at theoutput  
open condition.  
2. Address can be changed once or less while RAS = VIL.  
3. Measured with one sequential address change per EDO cycle, tHPC  
.
4. VIH VCC 0.2 V, 0 V VIL 0.2 V.  
Data Sheet E0098H10  
8