HM5216165 Series
Pin Functions
CLK (input pin):
CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS
(input pin):
When
CS
is Low, the command input cycle becomes valid. When
CS
is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS,
and
WE
(input pins):
Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A10 (input pins):
Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is
precharged.
A11 (input pin):
A11 is a bank select signal (BS). The memory array of the HM5216165 is divided into
bank 0 and bank 1, both which contain 2048 row
×
256 column
×
16 bits. If A11 is Low, bank 0 is selected,
and if A11 is High, bank 1 is selected.
CKE (input pin):
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down
and clock suspend modes.
DQMU/DQML (input pins):
DQMU controls upper byte and DQML controls lower byte input/output
buffers.
Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low,
the output buffer becomes Low-Z.
Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If
DQMU/DQML is Low, the data is written.
I/O0 to I/O15 (I/O pins):
Data is input to and output from these pins. These pins are the same as those of a
conventional DRAM.
EO
V
CC
and V
CC
Q (power supply pins):
3.3 V is applied. (V
CC
is for the internal circuit and V
CC
Q is for the
output buffer).
V
SS
and V
SS
Q (power supply pins):
Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for the
output buffer.)
L
Pr
Data Sheet E0167H10
od
uc
t
5
ELPIDA [ ELPIDA MEMORY ]
