HM5216165 Series
Self refresh entry [SELF]:
When this command is input during the IDLE state, the synchronous DRAM
starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low.
Since self refresh is performed internally and automatically, external refresh operations are unnecessary.
EO
Function Truth Table
Current state
Precharge
CS
H
L
L
L
L
L
L
L
L
Idle
H
L
L
L
L
L
L
L
L
Power down mode entry:
When this command is executed during the IDLE state, the synchronous DRAM
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self refresh exit:
When this command is executed during self refresh mode, the synchronous DRAM can
exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE
state.
Power down exit:
When this command is executed at the power down mode, the synchronous DRAM can
exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the IDLE
state.
The following table shows the operations that are performed when each command is issued in each mode of
the synchronous DRAM.
RAS CAS WE
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
×
L
H
H
H
L
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
Pr
Address
×
×
×
DESL
NOP
BST
BA, CA, A10
BA, CA, A10
BA, RA
×
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
MODE
ACTV
BA, A10
MODE
MRS
DESL
NOP
BST
ACTV
MRS
Command
Operation
Enter IDLE after t
RP
Enter IDLE after t
RP
NOP
ILLEGAL
READ/READ A
WRIT/WRIT A
Data Sheet E0167H10
9
od
ILLEGAL
ILLEGAL
NOP
PRE, PALL
REF, SELF
ILLEGAL
ILLEGAL
NOP
READ/READ A
WRIT/WRIT A
uc
NOP
NOP
ILLEGAL
ILLEGAL
Bank and row active
NOP
Refresh
PRE, PALL
REF, SELF
t
Mode register set
ELPIDA [ ELPIDA MEMORY ]
