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HM5212805FTD-75 参数 Datasheet PDF下载

HM5212805FTD-75图片预览
型号: HM5212805FTD-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 128M SDRAM接口的133 MHz / 100 MHz的2 Mword × 16位× 4银行/ 4 - Mword × 8位× 4银行PC / 133 , PC / 100 SDRAM [128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 62 页 / 554 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5212165FTD/HM5212805FTD-75/A60/B60
DQM Truth Table
(HM5212165F)
Command
Upper byte (DQ8 to DQ15) write enable/output enable ENBU
Lower byte (DQ0 to DQ7) write enable/output enable
ENBL
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU
Lower byte (DQ0 to DQ7) write inhibit/output disable
Note: H: V
IH
. L: V
IL
.
×:
V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
MASKL
DQM Truth Table
(HM5212805F)
Command
Write enable/output enable
Write inhibit/output disable
Note: H: V
IH
. L: V
IL
.
×:
V
IH
or V
IL
.
Write: I
DID
is needed.
Read: I
DOD
is needed.
The S DRA M ca n mask input/output data by mea ns of DQM, DQMU /D QML. DQMU masks the upper byte
and DQML masks the lower byte (HM5212165F).
Dur ing re ading, the output buff er is set to Low- Z by setting DQM, DQMU /D QML to Low, ena bling data
output. On the other hand, whe n DQM, DQMU /D QML is set to High, the output buff er bec omes High-Z,
disabling data output.
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set to
High, the pre vious data is held (the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or
burst write by setting DQM, DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of
the SDRAM operating instructions.
10
L
EO
CKE
Symbol
n-1
H
H
H
H
n
×
×
×
×
DQMU
L
×
H
×
DQML
×
L
×
H
CKE
n-1
H
n
×
×
DQM
L
H
Symbol
ENB
Data Sheet E0179H10
Pr
MASK
H
od
uc
t