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HM5212805FTD-75 参数 Datasheet PDF下载

HM5212805FTD-75图片预览
型号: HM5212805FTD-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 128M SDRAM接口的133 MHz / 100 MHz的2 Mword × 16位× 4银行/ 4 - Mword × 8位× 4银行PC / 133 , PC / 100 SDRAM [128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 62 页 / 554 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5212165FTD/HM5212805FTD-75/A60/B60
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]:
This command starts a wr ite oper ation. Whe n the
burst wr ite mode is sele cted, the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F )
and the bank sele ct addr ess (A 12/A 13) bec ome the burst wr ite start addr ess. Whe n the single wr ite mode is
selected, data is only written to the location specified by the column address (AY0 to AY8; HM5212165F, AY0
to AY9; HM5212805F) and the bank select address (A12/A13).
Writ e with au to-p re ch arge [WR IT A] :
This command automatica lly per forms a pre cha rge oper ation af ter a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this
command is illegal.
Row ad dr ess str obe an d b ank act ivate [A CTV ]:
This command ac tiva tes the bank that is sele cted by
A12/A13 (B S ) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2
is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by A12/A13.
If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low
and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation, the
one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM has a mode register that defines how it operates. The mode register is
spec ified by the addr ess pins (A 0 to A13) at the mode re giste r set cyc le. F or deta ils, re fe r to the mode re giste r
conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode re giste r set
command to set up the mode register.
L
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Data Sheet E0179H10
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